The present invention generally relates to methods of producing semiconductor memory devices, and more particularly to a method of producing an electrically erasable non-volatile memory.
In large scale semiconductor integrated circuit devices such as large scale integrated circuits (LSIs) and very large scale integrated circuits (VLSIs), electrically erasable non-volatile memories (EEPROMs) are provided as fixed memories in order to expand the functions thereof.
As will be described later on in the specification, an EEPROM cell unit comprises a transistor for selection and a memory transistor for storage, and write, erase and read operations are performed based on voltages which are applied to a bit line, a word line, a control gate, and a source of the EEPROM. Such an EEPROM occupies a large area in the LSI or VLSI, and it is necessary to reduce the area of the memory cells of the EEPROM in order to improve the integration density of the LSI and the VLSI.
A conventional method of producing the EEPROM will be described later in conjunction with the drawings. However, to explain the conventional method briefly, a gate oxide layer and a first resist layer are formed on a P-type silicon substrate. An opening is formed in the first resist layer, and impurity ions are implanted into the substrate through the gate oxide layer from the opening in the first resist layer so as to form an n-type impurity write/erase region in the substrate. Next, the first resist layer is removed, and a second resist layer is formed on the gate oxide layer. The second resist layer has an etching opening which has a shape corresponding to a tunnel region and is above the n-type impurity region. A reactive ion etching process is performed form, the etching opening so as to form in the gate oxide layer, an opening corresponding to the tunnel region.
Thereafter, the second resist layer is removed, and a thermal oxidation process is performed to form a tunnel oxide layer on a surface of the n-type impurity region which is exposed within the opening in the gate oxide layer. A first polysilicon layer is formed on the substrate, and a patterning process is performed. In addition, a silica dielectric layer is formed on the surface of the first polysilicon layer by a thermal oxidation process, and a second polysilicon layer is formed on the dielectric layer. The second polysilicon layer, the dielectric layer and the first polysilicon layer are simultaneously subjected to a patterning process so as to form a floating gate comprising the first polysilicon layer and a control gate comprising the second polysilicon layer. Next, n-type impurity ions are implanted into the substrate with a high concentration by using the control gate as a mask so as to form an n.sup.+ -type source region and an n.sup.+ -type drain region.
According to the conventional method described heretofore, the region where the tunnel oxide layer is formed, that is, the tunnel region, is formed on the top surface of the n-type impurity region by a mask alignment. However, when positioning the mask which is used to form the tunnel region with respect to the mask which is used to form the n-type impurity region, a positioning error is inevitably introduced. Accordingly, in order to ensure the formation of the tunnel region on the n-type impurity region regardless of whether the positioning error exists or not, the size of the n-type impurity region must be determined by taking into account a marginal space between two side edges of the n-type impurity region and two side edges of the tunnel region in accordance with the positioning error. On the other hand, the size of the tunnel region is determined by the size of the opening in the gate oxide layer. But, there is a limit in downsizing the opening in the gate oxide layer, and the opening in the gate oxide layer cannot be made extremely small. Hence, there is a limit in reducing the width of the tunnel region which is formed, and it is difficult to form the tunnel region with a width which is under one to two microns.
For these reasons, there is a problem in the conventional method in that it is difficult to further improve the integration density of the EEPROM by further downsizing the memory transistor.